Vivado is a design suite for Xilinx FPGA devices that provides a complete solution for creating, simulating, synthesizing, implementing, and verifying your design. Vivado 2017.2 is the latest release that supports a wide range of devices, including 3D ICs, SoCs, and UltraScale+ architectures.
In this article, we will show you how to download and install Vivado 2017.2, how to create a project and add files, how to customize and instantiate IP cores, how to perform pin assignments and timing constraints, how to run behavioral simulation and logic synthesis, and how to generate a bitstream and program your device.
To download Vivado 2017.2, you need to visit the Xilinx website at https://www.xilinx.com/support/download.html and click on the Vivado tab under the unified installer. You can choose between Windows or Linux versions, depending on your operating system. The download file is about 8.65 GB in size.
To install Vivado 2017.2, you need to run the installer and follow the instructions on the screen. You can choose between different editions of Vivado: WebPACK, Design Edition, or System Edition. WebPACK is a free edition that supports a limited number of devices, while Design Edition and System Edition are paid editions that support more devices and features. You can also select the components you want to install, such as documentation, SDK, HLS, etc.
If you already have Vivado 2017.2 installed and want to update it to Vivado 2017.2.1, which is a minor release that fixes some bugs and adds some enhancements, you can download the update file from the same website. The update file is about 3.7 GB in size and must be applied to an existing 2017.2 installation.
Creating a Project and Adding Files
To create a new project in Vivado 2017.2, you need to launch the Vivado IDE and select File > New Project from the menu bar. You will be guided through a series of steps to specify the project name, location, type (RTL or IP), device (family, package, speed grade), sources (HDL files or IP cores), constraints (XDC files), and simulation settings (language, library).
To add files to an existing project in Vivado 2017.2, you can either use the Add Sources wizard from the Flow Navigator pane or drag and drop files from the file browser into the Sources pane. You can also import files from other projects or tools using the Import wizard.
Customizing and Instantiating IP Cores
Vivado 2017.2 provides a rich set of IP cores that you can use in your design to implement common functions such as arithmetic operations, memory controllers, interfaces, etc. You can browse the IP catalog from the Flow Navigator pane or the IP Catalog window and select the IP core you want to use.
To customize an IP core in Vivado 2017.2, you need to double-click on it in the IP catalog or right-click on it and select Customize IP. You will see a customization window where you can modify the parameters of the IP core according to your needs. You can also view the documentation of the IP core by clicking on the Documentation button.
To instantiate an IP core in Vivado 2017.2, you need to click on the Generate button in the customization window or right-click on it and select Generate Output Products. This will create an HDL wrapper file that contains the instantiation template of the IP core with its ports and generics mapped to signals. You can then copy and paste this template into your top-level module or use it as a separate module in your design hierarchy.
Performing Pin Assignments and Timing Constraints
To perform pin assignments in Vivado 2017.2, you need to use the I/O Planning layout from the Layout menu bar or open it from the Flow Navigator pane. This layout shows a graphical representation of your device with its pins and banks. You can drag 06063cd7f5